1. Field of the Invention
The present invention relates to computer aided design (CAD) of integrated circuits, and more specifically to a method and apparatus for reducing the time to design an integrated circuit (IC) including performing electro-migration check.
2. Related Art
Integrated circuits are generally designed in multiple stages. For example, a high level design (e.g., in VHDL or Verilog languages, well known in the relevant arts) of an integrated circuit (IC) is synthesized (in a logic synthesis stage) to generate corresponding netlists (containing cells, interconnection details and power supply information). The cells are then placed in a placement stage.
The connections may then be performed first in a global routing stage (in which connections are established ignoring overlap type details) and then a detailed routing stage (in which the connections are routed through various metal layers to avoid overlap as well as to meet other design constraints). All these stages are often performed using corresponding design tools, potentially provided from different vendors (e.g., Cadence, Synopsis).
One of the tasks in such circuit design is electro-migration (EM) check. EM generally refers to dislodging of ions from a metal wire (connecting nodes in an IC), and is caused by current density (current flow divided by width of the metal) exceeding a corresponding threshold. EM impedes the ability of metal to conduct, in addition to leading to reduced life-time. Accordingly, it is generally desirable to ensure that current density does not exceed a desired threshold at least for a substantial amount of time. The related checks in design of ICs may be referred to as EM check.
In one prior embodiment, the EM checks are performed after the detailed routing stage noted above. One advantage of such an approach is that various details such as width (and other geometrical information) of paths (generally referred to as nets in the relevant arts) and expected current strength on the paths would readily be available after the detailed routing stage, and EM check can be easily performed. If a EM violation is detected for a path, the designer is often forced to perform tasks such as increasing the width of the path.
Such an approach may present several disadvantages. For example, increasing the path width can lead to violation of other constraints (e.g., cross-talk noise violation, congestion). Such additional problems may force the designers to revisit at least some of the stages iteratively. For example, a designer may manually attempt to re-route the path. If such re-routing cannot be performed, the designer may need to revisit the earlier design stages (e.g., placement). Such iterative approaches lead to increased design cycle time and costs, and is therefore undesirable at least in some environments.
What is therefore needed is a method and apparatus for reducing the time to design an integrated circuit (IC) including performing electro-migration check.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.